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ISO2-CMOS MT91L60/61 3 Volt Multi-Featured Codec (MFC)
Data Sheet Features
* * Single 2.7-3.6 volt supply operation MT91L61 version features a delayed framing pulse in SSI and ST-BUS modes to facilitate cascaded devices Programmable -Law/A-Law Codec and Filters Programmable ITU-T (G.711)/sign-magnitude coding Programmable transmit, receive and side-tone gains Fully differential interface to handset transducers - including 300 ohm receiver driver Flexible digital interface including ST-BUS/SSI Serial microport Low power operation ITU-T G.714 compliant Multiple power down modes
Ordering Information MT91L61AE 24 Pin PDIP MT91L60AE 24 Pin PDIP MT91L61AS 24 Pin SOIC MT91L60AS 20 Pin SOIC MT91L61AN 24 Pin SSOP MT91L60AN 20 Pin SSOP MT91L60ASR 20 Pin SOIC MT91L61ASR 24 Pin SOIC MT91L61ASR1 24 Pin SOIC* MT9160AN1 20 Pin SSOP* *Pb Free Matte Tin -40C to +85C
March 2006
* * * * * * * * *
Tubes Tubes Tubes Tubes Tubes Tubes
Tape & Reel Tape & Reel Tape & Reel Tubes
Applications
* * * * * * Battery operated equipment Digital telephone sets Cellular radio sets Local area communications stations Pair Gain Systems Line cards
VSSD VDD VSSA VBias VRef
FILTER/CODEC GAIN MENCODER DECODER 7dB -7dB Transducer Interface M+
HSPKR + HSPKR -
Din Dout STB/F0i CLOCKin STBd/FOod (MT91L61only) Flexible Digital Interface
Timing
ST-BUS C&D Channels Serial Microport A//IRQ
PWRST
IC
CS
DATA1
DATA2
SCLK
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MT91L60/61
Description
Data Sheet
The MT91L60/61 3 V Multi-featured Codec incorporates a built-in Filter/Codec, gain control and programmable sidetone path as well as on-chip anti-alias filters, reference voltage and bias source. The device supports both ITUT and sign- magnitude A-Law and -Law requirements. The MT91L60/61 is a true 3 V device employing a fully differential architecture to ensure wide dynamic range. Complete telephony interfaces are provided for connection to handset transducers. Internal register access is provided through a serial microport compatible with various industry standard micro-controllers. The MT91L60/61 is fabricated in Zarlink's ISO2-CMOS technology ensuring low power consumption and high reliability.
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Zarlink Semiconductor Inc.
MT91L60/61
MT91L60AS/AN
VBias VRef NC PWRST IC A//IRQ VSSD CS NC SCLK DATA1 DATA2
Data Sheet
MT91L60AE
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 M+ MVSSA NC HSPKR + HSPKR VDD CLOCKin NC STB/F0i Din Dout
MT91L61AE/AS/AN
VBias VRef NC PWRST IC A//IRQ VSSD CS NC SCLK DATA1 DATA2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 M+ MVSSA NC HSPKR + HSPKR VDD CLOCKin STBd/FOod STB/F0i Din Dout
VBias VRef PWRST IC A//IRQ VSSD CS SCLK DATA1 DATA2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
M+ MVSSA HSPKR + HSPKR VDD CLOCKin STB/F0i Din Dout
20 PIN SOIC/SSOP
24 PIN PDIP
24 PIN PDIP/SOIC/SSOP
Figure 2 - Pin Connections Pin Description Pin # 20 Pin24 Pin 1 2 3 4 5 1 2 4 5 6 Name VBias VRef Description Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 F capacitor to VSSA. Reference Voltage for Codec (Output). Used internally. Nominally [Vdd/2 - 1.1] volts. Connect 0.1 F capacitor to VSSA.
PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low). IC Internal Connection. Tie externally to VSSD for normal operation.
A//IRQ A/ - When internal control bit DEn = 0 this CMOS level compatible input pin governs the companding law used by the filter/Codec; -Law when tied to VSSD and A-Law when tied to VDD. Logically OR'ed with A/ register bit. IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt output signalling valid access to the D-Channel registers in ST-BUS mode. VSSD CS SCLK Digital Ground. Nominally 0 volts. Chip Select (Input). This input signal is used to select the device for microport data transfers. Active low. CMOS level compatible. Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level compatible.
6 7 8 9
7 8 10 11
DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/National mode of operation, this pin becomes the data transmit pin only and data receive is performed on the DATA 2 pin. Input CMOS level compatible. DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for data receive. In Intel mode, serial data transmit and receive are performed on the DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible. Dout Data Output. A high impedance three-state digital output for 8 bit wide channel data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent with the rising edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing.
10
12
11
13
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Zarlink Semiconductor Inc.
MT91L60/61
Pin Description (continued) Pin # 20 Pin24 Pin 12 14 Name Din Description
Data Sheet
Data Input. A digital input for 8 bit wide channel data received from the Layer 1 transceiver. Data is sampled on the falling edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. Input level is CMOS compatible.
13
15
STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate of 8 kHz. Standard frame pulse definitions apply in STBUS mode. CMOS level compatible input. STBd/F0 Delayed Frame Pulse Output. In SSI mode, an 8 bit wide strobe is output after the first strobe goes low. In ST-BUS mode, a frame pulse is output after 4 channel od (MT91L6 timeslots. 1 only) CLOCKin Clock (Input). The clock provided to this input pin is used for the internal device functions. For SSI mode connect the bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this input when the available bit clock is 128 kHz or 256 kHz. For ST-BUS mode connect C4i to this pin. CMOS level compatible. VDD Positive Power Supply (Input). Nominally 3 volts.
16
14
17
15 16 17 18 19 20
18 19 20 22 23 24 3,9, 16,21
HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced). HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker (balanced). VSSA MM+ NC Analog Ground (Input). Nominally 0 volts. Inverting Microphone (Input). Inverting input to microphone amplifier from the handset microphone. Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the handset microphone. No Connect. (24 Packages only). Pin 16 is NC for MT91L60.
Overview
The 3 V Multi-featured Codec (MFC) features complete Analog/Digital and Digital/Analog conversion of audio signals (Filter/Codec) and an analog interface to a standard handset transmitter and receiver (Transducer Interface). The receiver amplifier is capable of driving a 300 ohm load. Each of the programmable parameters within the functional blocks is accessed through a serial microcontroller port compatible with Intel MCS-51(R), Motorola SPI(R) and National Semiconductor Microwire(R) specifications. These parameters include: gain control, power down, mute, B-Channel select (ST-BUS mode), C&D channel control/access, law control, digital interface programming and loopback. Optionally the device may be used in a controllerless mode utilizing the power-on default settings.
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Zarlink Semiconductor Inc.
MT91L60/61
Functional Description
Filter/Codec
Data Sheet
The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are programmable. These are ITU-T G.711 A-law or -Law, with true-sign/Alternate Digit Inversion or true-sign/Inverted Magnitude coding, respectively. Optionally, sign-magnitude coding may also be selected for proprietary applications. The Filter/Codec block also implements transmit and receive audio path gains in the analog domain. A programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the handset receiver. This side tone path feature is disabled by default. Figure 3 depicts the nominal half-channel and side-tone gains for the MT91L60/61. In the event of PWRST, the MT91L60/61 defaults such that the side-tone path is off, all programmable gains are set to 0dB and ITU-T -Law is selected. Further, the digital port is set to SSI mode operation at 2048 kb/s and the FDI and driver sections are powered up. (See Microport section.) The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide dynamic range from a single 3 volt supply design. This fully differential architecture is continued into the Transducer Interface section to provide full chip realization of these capabilities for the handset functions. A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it may be used for biasing external gain setting amplifiers. A 0.1F capacitor must be connected from VBias to analog ground at all times. Although VRef may only be used internally, a 0.1F capacitor must be connected from VRef to ground. The analog ground reference point for these two capacitors must be physically the same point. To facilitate this the VRef and VBias pins are situated on adjacent pins. The transmit filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain control = 0 dB). Gain control allows the output signal to be increased up to 7 dB. An anti-aliasing filter is included. This is a second order lowpass implementation with a corner frequency at 25 kHz. The receive filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain control = 0 dB). Gain control allows the output signal to be attenuated up to 7 dB. Filter response is peaked to compensate for the sinx/x attenuation caused by the 8 kHz sampling rate. Side-tone is derived from the input of the Tx filter and is not subject to the gain control of the Tx filter section. Sidetone is summed into the receive handset transducer driver path after the Rx filter gain control section so that Rx gain adjustment will not affect side-tone levels. The side-tone path may be enabled/disabled with the gain control bits located in Gain Control Register 2 (address 01h). Transmit and receive filter gains are controlled by the TxFG0-TxFG2 and RxFG0-RxFG2 control bits, respectively. These are located in Gain Control Register 1 (address 00h). Transmit filter gain is adjustable from 0dB to +7dB and receive filter gain from 0dB to -7dB, both in 1dB increments. Side-tone filter gain is controlled by the STG0-STG2 control bits located in Gain Control Register 2 (address 01h). Side-tone gain is adjustable from -9.96 dB to +9.96 dB in 3.32 dB increments. Companding law selection for the Filter/Codec is provided by the A/ companding control bit while the coding scheme is controlled by the Smag/ITU-T control bit. The A/ control bit is logically OR'ed with the A/ pin providing access in both controller and controllerless modes. Both A/ and Smag/ITU-T reside in Control Register 2 (address 04h). Table 1 illustrates these choices.
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Zarlink Semiconductor Inc.
MT91L60/61
Sign/ Magnitude
1111 1111 1000 0000 0000 0000 0111 1111
Data Sheet
Code
+ Full Scale + Zero -Zero (quiet code) - Full Scale
ITU-T (G.711) -Law
1000 0000 1111 1111 0111 1111 0000 0000
A-Law
1010 1010 1101 0101 0101 0101 0010 1010
Table 1 Transducer Interfaces Standard handset transducer interfaces are provided by the MT91L60/61. These are: * The handset microphone inputs (transmitter), pins M+/M-. The nominal transmit path gain may be adjusted to either 6.0 dB or 15.3 dB. Control of this gain is provided by the TxINC control bit (Gain Control register 1, address 00h). The handset speaker outputs (receiver), pins HSPKR+/HSPKR-. This internally compensated fully differential output driver is capable of driving the load shown in Figure 3. The nominal receive path gain may be adjusted to either 0 dB, -6 dB or -12 dB. Control of this gain is provided by the RxINC control bit (Gain Control register 1, address 00h). This gain adjustment is in addition to the programmable gain provided by the receive filter.
*
Serial
Port
Filter/Codec and Transducer Interface
Default Bypass -6.0 dB or 0 dB Receiver Driver HSPKR + 75 HSPKR 75 Side-tone -9.96 to +9. 96 dB (3.32 dB steps) Default Side-tone off Handset Receiver (150)
PCM
Din
Decoder
Receive Filter Gain 0 to -7 dB (1 dB steps)
-6 dB
-11 dB
PCM
Dout
Encoder
Transmit Filter Gain Gain 0 0(1 dB+7dB toto steps) +7 dB
Transmit Gain -0.37 dB or 8.93 dB
Transmit Gain 6.37 dB
M+ M-
Transmitter Microphone
Internal To Device
External To Device
Figure 3 - Audio Gain Partitioning
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Zarlink Semiconductor Inc.
MT91L60/61
Microport
Data Sheet
The serial microport, compatible with Intel MCS-51 (mode 0), Motorola SPI (CPOL=0,CPHA=0) and National Semiconductor Microwire specifications provides access to all MT91L60/61 internal read and write registers. This microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a synchronous data clock pin (SCLK). For D-channel contention control, in ST-BUS mode, this interface provides an open-drain interrupt output (IRQ). The microport dynamically senses the state of the serial clock (SCLK) each time chip select becomes active. The device then automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National requirements. If SCLK is high during chip select activation then Intel mode 0 timing is assumed. The DATA1 pin is defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during chip select activation then Motorola/National timing is assumed. Motorola processor mode CPOL=0, CPHA=0 must be used. DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. Although the dual port Motorola controller configuration usually supports full-duplex communication, only half-duplex communication is possible in the MT91L60/61. The micro must discard non-valid data which it clocks in during a valid write transfer to the MT91L60/61. During a valid read transfer from the MT91L60/61 data simultaneously clocked out by the micro is ignored by the MT91L60/61. All data transfers through the microport are two-byte transfers requiring the transmission of a Command/Address byte followed by the data byte written or read from the addressed register. CS must remain asserted for the duration of this two-byte transfer. As shown in Figures 5 and 6 the falling edge of CS indicates to the MT91L60/61 that a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the MT91L60/61 and the microcontroller. At the end of the two-byte transfer CS is brought high again to terminate the session. The rising edge of CS will tri-state the output driver of DATA1 which will remain tri-stated as long as CS is high. Intel processors utilize least significant bit first transmission while Motorola/National processors employ most significant bit first transmission. The MT91L60/61 microport automatically accommodates these two schemes for normal data bytes. However, to ensure decoding of the R/W and address information, the Command/Address byte is defined differently for Intel operation than it is for Motorola/National operation. Refer to the relative timing diagrams of Figures 5 and 6. Receive data is sampled on the rising edge of SCLK while transmit data is made available concurrent with the falling edge of SCLK.
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Zarlink Semiconductor Inc.
MT91L60/61
Data Sheet
COMMAND/ADDRESS 5)
1)
DATA INPUT/OUTPUT
1)
4) COMMAND/ADDRESS:
DATA 1 RECEIVE D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
DATA 1 TRANSMIT SCLK 2)
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
CS 3) 1) Delays due to internal processor timing which are transparent.
4) 3)
2) The MT91L60/L61:latches received data on the rising edge of SCLK. -outputs transmit data on the falling edge of SCLK. 3) The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data until terminated via CS returning high. 4) A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. D7 1 bit - Read/Write 5) The COMMAND/ADDRESS byte contains: 3 bits - Addressing Data X X X X A2 4 bits - Unused
D0 A1 A0 R/W
Figure 4 - Audio Gain Partitioning
COMMAND/ADDRESS 5)
1)
DATA INPUT/OUTPUT
1)
4) COMMAND/ADDRESS:
DATA 2 RECEIVE D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DATA 1 TRANSMIT SCLK 2)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CS 3)
4) 3)
1) Delays due to internal processor timing which are transparent. 2) The MT91L60/L61: latches received data on the rising edge of SCLK. -outputs transmit data on the falling edge of SCLK. 3) The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data until terminated via CS returning high. 4) A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. D7 1 bit - Read/Write 5) The COMMAND/ADDRESS byte contains: 3 bits - Addressing Data A2 4 bits - Unused X X R/W X
D0 A1 A0 X
Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
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Zarlink Semiconductor Inc.
MT91L60/61
Flexible Digital Interface
Data Sheet
A serial link is required to transport data between the MT91L60/61 and an external digital transmission device. The MT91L60/61 utilizes the ST-BUS architecture defined by Zarlink Semiconductor but also supports a strobed data interface found on many standard Codec devices. This interface is commonly referred to as Simple Serial Interface (SSI). The combination of ST-BUS and SSI provides a Flexible Digital Interface (FDI) capable of supporting all Zarlink basic rate transmission devices as well as many other 2B+D transceivers. The required mode of operation is selected via the CSL2-0 control bits (Control Register 2, address 04h). Pin definitions alter dependent upon the operational mode selected, as described in the following subsections as well as in the Pin Description tables. Quiet Code The FDI can be made to send quiet code to the decoder and receive filter path by setting the RxMute bit high. Likewise, the FDI will send quiet code in the transmit path when the TxMute bit is high. Both of these control bits reside in Control Register 1 at address 03h. When either of these bits are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet code definition. ST-BUS Mode The ST-BUS consists of output (DSTo) and input (DSTi) serial data streams, in FDI these are named Dout and Din respectively, a synchronous clock input signal CLOCKin (C4i), and a framing pulse input (F0i). These signals are direct connections to the corresponding pins of Zarlink basic rate devices. The CSL2, CSL1 and CSL0 bits are set to 1 for ST-BUS operation. The data streams operate at 2048 kb/s and are Time Division Multiplexed into 32 identical channels of 64 kb/s bandwidth. A frame pulse (a 244 nSec low going pulse) is used to separate the continuous serial data streams into the 32 channel TDM frames. Each frame has a 125 Second period translating into an 8 kHz frame rate. A valid frame begins when F0i is logic low coincident with a falling edge of C4i. Refer to Figure 11 for detailed ST-BUS timing. C4i has a frequency (4096 kHz) which is twice the data rate. This clock is used to sample the data at the 3/4 bit-cell position on DSTi and to make data available on DSTo at the start of the bit-cell. C4i is also used to clock the MT91L60/61 internal functions (i.e., Filter/Codec, Digital gain and tone generation) and to provide the channel timing requirements. The MT91L60/61 uses only the first four channels of the 32 channel frame. These channels are always defined, beginning with Channel 0 after the frame pulse, as shown in Figure 6 (ST-BUS channel assignments). The MT91L60/61 provides a delayed frame pulse (F0od), 4 channels after the input frame pulse. The first two (D & C) Channels are enabled for use by the DEN and CEN bits respectively, (Control Register 2, address 04h). ISDN basic rate service (2B+D) defines a 16 kb/s signalling (D) Channel. The MT91L60/61 supports transparent access to this signalling channel. ST-BUS basic rate transmission devices, which may not employ a microport, provide access to their internal control/status registers through the ST-BUS Control (C) Channel. The MT91L60/61 supports microport access to this C-Channel.
125 s F0i DSTi, DSTo
CHANNEL 0 D-channel LSB first for DChannel
CHANNEL 1 C-channel
CHANNEL 2 B1-channel
CHANNEL 3 B2-channel
CHANNELS 4-31 Not Used
MSB first for C, B1- & B2Channels
FOod
Figure 6 - ST-BUS Channel Assignment
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Zarlink Semiconductor Inc.
MT91L60/61
DEN - D-Channel
Data Sheet
In ST-BUS mode access to the D-Channel (transmit and receive) data is provided through an 8-bit read/write register (address 06h). D-Channel data is accumulated in, or transmitted from this register at the rate of 2 bits/frame for 16 kb/s operation (1 bit/frame for 8 kb/s operation). Since the ST-BUS is asynchronous, with respect to the microport, valid access to this register is controlled through the use of an interrupt (IRQ) output. D-Channel access is enabled via the (DEn) bit. DEN: When 1, ST-BUS D-channel data (1 or 2 bits/frame depending on the state of the D8 bit) is shifted into/out of the Dchannel (READ/WRITE) register. When 0, the receive D-channel data (READ) is still shifted into the proper register while the DSTo D-channel timeslot and IRQ outputs are tri-stated (default). D8: When 1, D-Channel data is shifted at the rate of 1 bit/frame (8 kb/s). When 0, D-Channel data is shifted at the rate of 2 bits/frame (16 kb/s default). 16 kb/s D-Channel operation is the default mode which allows the microprocessor access to a full byte of DChannel information every fourth ST-BUS frame. By arbitrarily assigning ST-BUS frame n as the reference frame, during which the microprocessor D-Channel read and write operations are performed, then: a. A microport read of address 04 hex will result in a byte of data being extracted which is composed of four I-bits (designated by roman numerals I,II,III,IV). These di-bits are composed of the two D-Channel bits received during each of frames n, n-1, n-2 and n-3. Referring to Fig. 7a: di-bit I is mapped from frame n3, di-bit II is mapped from frame n-2, di-bit III is mapped from frame n-1 and di-bit IV is mapped from frame n. The D-Channel read register is not preset to any particular value on power-up (PWRST) or software reset (RST). b. A microport write to Address 04 hex will result in a byte of data being loaded which is composed of four di-bits (designated by roman numerals I, II, III, IV). These di-bits are destined for the two D-Channel bits transmitted during each of frames n+1, n+2, n+3, n+4. Referring to Fig. 7a: di-bit I is mapped to frame n+1, di-bit II is mapped to frame n+2, di bit III is mapped to frame n+3 and di bit IV is mapped to frame n+4. If no new data is written to address 04 hex, the current D-channel register contents will be continuously retransmitted. The D-Channel write register is preset to all ones on power-up (PWRST) or software reset (RST). An interrupt output is provided (IRQ) to synchronize microprocessor access to the D-Channel register during valid ST-BUS periods only. IRQ will occur every fourth (eighth in 8 kb/s mode) ST-BUS frame at the beginning of the third (second in 8 kb/s mode) ST-BUS bit cell period. The interrupt will be removed following a microprocessor Read or Write of Address 04 hex or upon encountering the following frames F0i input, whichever occurs first. To ensure DChannel data integrity, microport read/write access to Address 04 hex must occur before the following frame pulse. See Figure 7b for timing. 8 kb/s operation expands the interrupt to every eight frames and processes data one-bit-per-frame. D-Channel register data is mapped according to Figure 7c. CEn - C-Channel Channel 1 conveys the control/status information for the Layer 1 transceiver. C-Channel data is transferred MSB first on the ST-BUS by the MT91L60/61. The full 64 kb/s bandwidth is available and is assigned according to which transceiver is being used. Consult the data sheet for the selected transceiver for its C-Channel bit definitions and order of bit transfer.
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Zarlink Semiconductor Inc.
MT91L60/61
Data Sheet
When CEN is high, data written to the C-Channel register (address 05h) is transmitted, most significant bit first, on DSTo. On power-up reset (PWRST) or software reset (Rst, address 03h) all C-Channel bits default to logic high. Receive C-Channel data (DSTi) is always routed to the read register regardless of this control bit's logic state. When low, data transmission is halted and this timeslot is tri-stated on DSTo. B1-Channel and B2-Channel Channels 2 and 3 are the B1 and B2 channels, respectively. B-channel PCM associated with the Filter/Codec and transducer audio paths is selected on an independent basis for the transmit and receive paths. TxBSel and RxBSel (Control Register 1, address 03h) are used for this purpose. If no valid transmit path has been selected then the timeslot output on DSTo is tri-stated (see PDFDI and PDDR control bits, Control Register 1 address 03h).
IRQ Microport Read/Write Access FP n-3 n-2 n-1 n n+1 n+2 n+3 n+4*
DSTo/ DSTi Di-bit Group Receive D-Channel
D0
I
II D1 D2 No preset value
D3
D4
III
D5
IV D6 D7 Di-bit Group Transmit D-Channel
D0
I D1 D2
II
D3
D4
III
D5
D6
IV
D7
Power-up reset to 1111 1111
* note that frame n+4 is equivalent to frame n of the next cycle.
Figure 7a - D-Channel 16 kb/s Operation
FP
C4i
C2 tir =500 nsec max Rpullup= 10 k tif =500 nsec max IRQ 8 kb/s operation 16 kb/s operation Microport Read/Write Access
Reset coincident with Read/Write of Address 04 Hex or next FP, whichever occurs first
DSTo/ DSTi
D0
D1
Figure 7b - IRQ Timing Diagram
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Zarlink Semiconductor Inc.
MT91L60/61
Data Sheet
IRQ
Microport Read/Write Access FP
n-7 n-6 n-5 n-4 n-3 n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8
D-Channel Di-bit Group Receive D-Channel
I D0 II D1 III D2 IV D3 V D4 VI D5 VII D6 VIII D7 I D0 II D1 III D2 IV D3 V D4 VI D5 VII D6 VIII D7
No preset value
Di-bit Group Transmit D-Channel
Power-up reset to 1111 1111
Figure 7c - D-Channel 8 kb/s Operation SSI Mode The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input signal (CLOCKin), and a framing strobe input (STB). The frame strobe must be synchronous with, and eight cycles of, the bit clock. A 4.096 MHz master clock is also required for SSI operation if the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 12 & 13. In SSI mode the MT91L60/61 supports only B-Channel operation. The internal C and D Channel registers used in ST-BUS mode are not functional for SSI operation. The control bits TxBSel and RxBSel, as described in the STBUS section, are ignored since the B-Channel timeslot is defined by the input STB strobe. Hence, in SSI mode transmit and receive B-Channel data are always in the channel defined by the STB input. The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This is an active high signal with an 8 kHz repetition rate. The MT91L61 provides a delayed strobe pulse which occurs after the initial strobe goes low and is held high for the duration of 8 pcm bits. SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is 512 kHz or greater then it is used directly by the internal MT91L60/61 functions allowing synchronous operation. If the available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal MT91L60/61 functions. Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT91L60/61 will realign its internal clocks to allow operation when the external master and bit clocks are asynchronous. Control bits CSL2, CSL1 and CSL0 in Control Register 2 (address 04h) are used to program the bit rates. For synchronous operation data is sampled, from Din, on the falling edge of BCL during the time slot defined by the STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input. Dout is tri-stated at all times when STB is not true. If STB is valid and PDDR is set, then quiet code will be transmitted on Dout during the valid strobe period. There is no frame delay through the FDI circuit for synchronous operation. For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed output jitter on Dout is larger. This is due to the resynchronization circuitry activity and will not affect operation since the bit cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the FDI circuit for asynchronous operation. Refer to the specifications of Figures 12 & 13 for both synchronous and asynchronous SSI timing.
12
Zarlink Semiconductor Inc.
MT91L60/61
PWRST/Software Reset (Rst)
Data Sheet
While the MT91L60/61 is held in PWRST no device control or functionality is possible. While in software reset (Rst=1, address 03h) only the microport is functional. Software reset can only be removed by writing the Rst bit low or by performing a hardware PWRST. While the Rst bit is high, the other bits in Control Register 1 are held low and cannot be reprogrammed. Therefore to modify Control Register 1 the Rst bit must first be written low, followed by a 2nd write operation which writes the desired data. This avoids a race condition between clearing the reset bit and the writing of the other bits in Control Register 1. After a Power-up reset (PWRST) or software reset (Rst) all control bits assume their "Power Reset Value" default states; -Law coding, 0 dB Rx and 6dB Tx gains and the device powered up in SSI mode 2048 kb/s operation with Dout tri-stated while there is no strobe active on STB. If a valid strobe is supplied to STB, then Dout will be active, during the defined channel. To attain complete power-down from a normal operating condition, write PDFDI = 1 and PDDR = 1 (Control Register 1, address 03h) or set the PWRST pin low. 00 01 02 03 04 05 06 07 RxINC PDFDI CEN C7 D7 RxFG2 PDDR DEN C6 D6 RxFG1 RST D8 C5 D5 RxFG0 A/ C4 D4 TxINC TxMute Smag/ ITU-T C3 D3 PCM/ ANALOG TxFG2 STG2 RxMute CSL2 C2 D2 loopen TxFG1 STG1 TxBsel CSL1 C1 D1 TxFG0 STG0 DrGain Gain Control Register 1 Gain Control Register 2 Path Control
RxBsel Control Register 1 CSL0 C0 D0 Control Register 2 C-Channel Register D-Channel Register Loop Back
Table 2 - 3V Multi-featured Codec Register Map
Note: Bits marked "-" are reserved bits and should be written with logic "0"
13
Zarlink Semiconductor Inc.
MT91L60/61
Applications
Data Sheet
Figure 8 shows an application in a wireless phone set. Figure 9 shows an MT9161B's delayed frame pulse driving a second MT9161B. This configuration would be used where multiple CODEC's were using a data bus (an example being Zarlink's ST-BUS).
330 + 10 F 511 +3V 0.1 F 100K VBias 0.1 F 100K 511 + Differential Amplifier 0.1 F VBias M+ R T Av = 1 + 2R T R Single-ended Amplifier M+ 10 F + Electret Microphone + 1K 330 +3V 0.1 F
T R
VBias
+ -
M+
+ Electret Microphone
VBias
M-
(
Typical External Gain AV= 5-10
)
M+ M-
0.1 F 0.1 F 100K +3V A//IRQ 3V INTEL MCS-51 or MOTOROLA SPI MicroController CS SCLK DATA1 DATA2 DATA2 Motorola Mode only 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
75
MT91L60
+3V
150 75
Din Wireless Phone Baseband Processer Frame Pulse Dout
Clock
Figure 8 - Wireless Phone Set
14
Zarlink Semiconductor Inc.
MT91L60/61
Data Sheet
0.1 F
VBias
(
1 2 3 4
Typical External Gain AV= 5-10
)
M+ M-
0.1 F 0.1 F 100K +3V A//IRQ 3V INTEL MCS-51 or MOTOROLA SPI MicroController CS SCLK DATA1 DATA2 DATA2 Motorola Mode only
24 23 22 21 20 19 18 17 16 15 14 13 75
5 6 7 8 9 10 11 12
MT91L61
+3V
150 75
Din Dout Timing from PC Bus Clock 0.1 F VBias MM+ 0.1 F 1 +3V 2 3 4 A//IRQ CS SCLK DATA1 DATA2 DATA2 Motorola Mode only 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 75 Frame Pulse
MT91L61
+3V
75
150
Figure 9 - Delayed Frame Pulse of First MT91L61 Signalling Second MT91L61
15
Zarlink Semiconductor Inc.
MT91L60/61
Register Summary
Gain Control Register 1
Data Sheet
ADDRESS = 00h WRITE/READ VERIFY
Power Reset Value 1000 0000
RxINC RxFG2 RxFG1 RxFG0 TxINC TxFG2 TxFG1 TxFG0 7 6 5 4 3 2 1 0
Receive Gain Setting (dB) (default) 0 -1 -2 -3 -4 -5 -6 -7
RxFG2 0 0 0 0 1 1 1 1
RxFG1 0 0 1 1 0 0 1 1
RxFG0 0 1 0 1 0 1 0 1
Transmit Gain Setting (dB) (default) 0 1 2 3 4 5 6 7
TxFG2 0 0 0 0 1 1 1 1
TxFG1 0 0 1 1 0 0 1 1
TxFG0 0 1 0 1 0 1 0 1
RxFGn = Receive Filter Gain bit n
TxFGn = Transmit Filter Gain bit n
RxINC: When high, the receive path nominal gain is set to 0 dB. When low, this gain is -6.0 dB. TxINC: When high, the transmit path nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB.
Gain Control Register 2 7 6 5 4
-
ADDRESS = 01h WRITE/READ VERIFY STG2 2 STG1 1 STG0 0
Power Reset Value XXXX X000
3
Side-tone Gain Setting (dB) (default) OFF -9.96 -6.64 -3.32 0 3.32 6.64 9.96 STGn = Side-tone Gain bit n
STG2 0 0 0 0 1 1 1 1
STG1 0 0 1 1 0 0 1 1
STG0 0 1 0 1 0 1 0 1
Note: Bits marked "-" are reserved bits and should be written with logic "0"
16
Zarlink Semiconductor Inc.
MT91L60/61
Path Control
Data Sheet
ADDRESS = 02h WRITE/READ VERIFY 7 6 5 4
-
2
1
DrGain 0
Power Reset Value XX00 0000
3
DrGain
When high, the receive path is summed with the side tone path and is attenuated by 6dB. When low, the receive path contains no side tone (default).
Control Register 1 _ 4
ADDRESS = 03h WRITE/READ VERIFY Rst 5
TxMute RxMute TxBsel RxBsel
Power Reset Value 0000 0000
PDFDI PDDR 7
PDFDI PDDR
6
3
2
1
0
Rst
TxMute
RxMute TxBsel RxBsel
When high, the FDI PLA and the Filter/Codec are powered down (default). When low, the FDI is active. When high, the ear driver and Filter/Codec are powered down (default). In addition, in ST-BUS mode, the selected output channel is tri-stated. In SSI mode the PCM output code will be -zero code during the valid strobe period. The output will be tri-stated outside of the valid strobe and for the whole frame if no strobe is supplied. When low, the driver and Filter/Codec are active if PDFDI is low. When high, a software reset occurs performing the same function as the hardware reset (PWRST) except that the Rst bit remains high and device remains powered up. A software reset can be removed only by writing this bit low or by means of a hardware reset (PWRST). This bit is useful for quickly programming the Registers to the default Power Reset Values. When this bit is low, the reset condition is removed allowing the registers to be modified When high the transmit PCM stream is interrupted and replaced with quiet code; thus forcing the output code into a mute state (only the output code is muted, the transmit microphone and transmit Filter/Codec are still functional). When low the full transmit path functions normally (default). When high the received PCM stream is interrupted and replaced with quiet code; thus forcing the receive path into a mute state. When low the full receive path functions normally (default). When high, the transmit B2 channel is functional in ST-BUS mode. When low, the transmit B1 channel is functional in ST-BUS mode. Not used in SSI mode. When high, the receive B2 channel is functional in ST-BUS mode. When low, the receive B1 channel is functional in ST-BUS
Note: Bits marked "-" are reserved bits and should be written with logic "0"
17
Zarlink Semiconductor Inc.
MT91L60/61
Control Register 2 CEn 7
CEn
Data Sheet
ADDRESS = 04h WRITE/READ VERIFY
DEn 6
D8 5
A/ 4
Smag/ ITU-T
CSL2 2
CSL1 1
CSL0 0
Power Reset Value 0000 0010
3
DEn
D8 A/ Smag/ITU-T
When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When low, the channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel register (address 05h) regardless of the state of CEn. This control bit has significance only for ST-BUS operation and is ignored for SSI operation. When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0 on DSTo. The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is completely tri-stated on DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of the state of DEN. This control bit has significance only for ST-BUS mode and is ignored for SSI operation. When high, D-channel operates at 8 kb/s. When low, D-channel operates at 16 kb/s (default). When high, A-Law encoding/decoding is selected for the MT91L60/61. When low, -Law encoding/decoding is selected. When high, sign-magnitude code assignment is selected for the Codec input/output. When low, ITU-T code assignment is selected for the Codec input/output; true sign, inverted magnitude (-Law) or true sign, alternate digit inversion (A-Law). CSL2 1 1 1 0 0 0 0 CSL1 1 0 0 0 0 1 1 CSL0 1 0 1 0 1 0 1 Bit Clock rate (kHz) N/A 128 256 512 1536 2048 4096 CLOCKin (kHz) 4096 4096 4096 512 1536 2048 4096 Mode ST-BUS SSI SSI SSI SSI SSI (default) SSI
Note: Bits marked "-" are reserved bits and should be written with logic "0"
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Zarlink Semiconductor Inc.
MT91L60/61
C-Channel Register C7 7 C6 6 C5 5 C4 4 C3 3 C2 2 C1 1 C0 0
Data Sheet
ADDRESS = 05h WRITE/READ
Power Reset Value 1111 1111- write XXXX XXXX - read
Micro-port access to the ST-BUS C-Channel information read and write
D-Channel Register
ADDRESS = 06h WRITE/READ D6 6 D5 5 D4 4 D3 3 D2 2 D1 1 D0 0
Power Reset Value 1111 1111- write XXXX XXXX - read
D7 7
D7-D0
Data written to this register will be transmitted every frame, in channel 0, if the DEn control bit is set (address 04h). Received DChannel data is valid, regardless of the state of DEn. These bits are valid for ST-BUS mode only and are accessible only when IRQ indicates valid access.
Loopback Register 7 6 5 4
PCM/ ANALOG
ADDRESS = 07h WRITE/READ VERIFY
loopen
1
0
Power Reset Value XXXX 0000
3
2
PCM/ANALOG This control bit functions only when loopen is set high. It is ignored when loopen is low. For loopback operation when this bit is high, the device is configured for digital-to-digital loopback operation. Data on Din is looped back to Dout without conversion to the analog domain. However, the receive D/A path (from Din to HSPKR ) still functions. When low, the device is configured for analog-to-analog operation. An analog input signal at M is looped back to the SPKR outputs through the A/D and D/A circuits as well as through the normal transmit A/D path (from M to Dout). loopen When high, loopback operation is enabled and the loopback type is governed by the state of the PCM/ANALOG bit. When low, loopbacks are disabled, the device operates normally and the PCM/ANALOG bit is ignored.
Note: Bits marked "-" are reserved bits and should be written with logic "0"
HSPKR +/-
Din
HSPKR +/-
Dout
M +/-
Dout
Analog Loopback PCM/ANALOG = 0 loopen = 1
Digital Loopback PCM/ANALOG = 1 loopen = 1
Figure 10 - Loopback Signal Flow
19
Zarlink Semiconductor Inc.
MT91L60/61
Absolute Maximum Ratings Parameter 1 2 3 4 5
Data Sheet
Symbol VDD - VSS VI/VO II/IO TS PD
Min. - 0.3 VSS - 0.3
Max. 5 VDD + 0.3 20
Units V V mA C mW
Supply Voltage Voltage on any I/O pin Current on any I/O pin (transducers excluded) Storage Temperature Power Dissipation (package)
- 65
+ 150 750
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated Characteristics 1 2 3 4 Supply Voltage CMOS Input Voltage (high) CMOS Input Voltage (low) Operating Temperature Sym. VDD VIHC VILC TA Min. 2.7 0.9*VDD VSS - 40 Typ. 3 Max. 3.6 VDD 0.1*VDD + 85 Units V V V C Test Conditions
Power Characteristics Characteristics 1 Static Supply Current (clock disabled, all functions off, PDFDI/PDDR=1, PWRST=0) Dynamic Supply Current: Total all functions enabled Sym. IDDC1 Min. Typ. 2 Max. 20 Units A Test Conditions Outputs unloaded, Input signals static, not loaded See Note 1.
2
IDDFT
6
10
mA
Note 1: Power delivered to the load is in addition to the bias current requirements.
20
Zarlink Semiconductor Inc.
MT91L60/61
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 Input HIGH Voltage CMOS inputs Input LOW Voltage CMOS inputs VBias Voltage Output VRef Voltage Output Input Leakage Current Positive Going Threshold Voltage (PWRST only) Negative Going Threshold Voltage (PWRST only) Hysteresis Output HIGH Current Output LOW Current Output Leakage Current Output Capacitance Input Capacitance Sym. VIHC VILC VBias VRef IIZ VT+ VT0.65 IOH IOL IOZ Co Ci 1.0 2.5 0.01 15 10 10 2.2 0.7 VDD/2 VDD/2-1.1 0.1 10 Min.
0.7*Vdd 0.3*Vdd
Data Sheet
Typ.
Max.
Units V V V V mA V V V mA mA mA pF pF
Test Conditions
Max. Load = 20k No Load VIN=VDD to VSS Vdd = 3V
7 8 9 10 11
VOH = 0.9*VDD See Note 1 VOL = 0.1*VDD See Note 1 VOUT = VDD and VSS
DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. * Note 1 - Magnitude measurement, ignore signs.
Clockin Tolerance Characteristics (ST-BUS Mode) Characteristics 1 C4i Frequency Min. 4095.6 Typ. 4096 Max. 4096.4 Units kHz Test Conditions (i.e., 100 ppm)
AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing.
21
Zarlink Semiconductor Inc.
MT91L60/61
Data Sheet
AC Characteristics for A/D (Transmit) Path - 0 dBm0 = ALo3.17 - 3.17 dB = 1.027 Vrms for -Law and 0 dBm0 = ALo3.14 3.14 dB =1.067 Vrms for A-Law, at the Codec. (VRef = 0.4 V and VBias=1.5 volts.) Characteristics 1 Analog input equivalent to overload decision Absolute half-channel gain M to Dout GAX1 GAX2 5.4 14.7 -0.2 6.0 15.3 0.1 6.6 15.9 +0.2 dB dB dB Sym. ALi3.17 ALi3.14 Min. Typ. 4.246 4.4 Max. Units Vp-p Vp-p Test Conditions -Law A-Law Both at Codec Transmit filter gain=0 dB setting. TxINC = 0* TxINC = 1* @1020 Hz
2
Tolerance at all other transmit filter settings (1 to 7 dB) 3 Gain tracking vs. input level ITU-T G.714 Method 2 Signal to total Distortion vs. input level. ITU-T G.714 Method 2 Transmit Idle Channel Noise Gain relative to gain at 1020 Hz <50 Hz 60 Hz 200 Hz 300 - 3000 Hz 3000-3300 Hz 3300 Hz 3400 Hz 4000 Hz 4600 Hz >4600 Hz Absolute Delay Group Delay relative to DAX GTX
-0.3 -0.6 -1.6 35 29 24 13 -70.5
0.3 0.6 1.6
dB dB dB dB dB dB
3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0 -Law A-Law
4
DQX
5 6
NCX NPX GRX
16 -69 -25 -30 0.0 0.25 0.25 0.25 0.25 -12.5 -25 -25
dBrnC0 dBm0p dB dB dB dB dB dB dB dB dB dB ms ms ms ms ms
-45 -0.25 -0.9 -0.9 -1.2
-0.2 -0.6 -23 -41 360 750 380 130 750
7 8
DAX DDX
at frequency of minimum delay 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz 100 mV peak signal on VDD -law
9
Power Supply Rejection f=1020 Hz PSSR 30 50 dB
AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. * Note: TxINC, refer to Control Register 1, address 00h.
22
Zarlink Semiconductor Inc.
MT91L60/61
Data Sheet
AC Characteristics for D/A (Receive) Path - 0 dBm0 = ALo3.17 - 3.17 dB = 1.027 Vrms for -Law and 0 dBm0 = ALo3.14 - 3.14 dB
=1.067 Vrms for A-Law, at the Codec. (VRef = 0.4 V and VBias=1.5 volts.)
Characteristics 1 2 Analog output at the Codec full scale Absolute half-channel gain. Din to HSPKR
Sym. ALo3.17 ALo3.14 GAR1 GAR2 GAR3 GAR4
Min.
Typ. 4.183 4.331
Max.
Units Vp-p Vp-p
Test Conditions -Law A-Law DrGain=0, RxINC =1* DrGain=0, RxINC =0* DrGain=1, RxINC =1* DrGain=1, RxINC =0* @ 1020 Hz
-0.6 -6.6 -6.6 -12.6 -0.2
0 -6 -6 -12 0.1
0.6 -5.4 -5.4 -11.4 +0.2
dB dB dB dB dB
Tolerance at all other receive filter settings (-1 to -7 dB) 3 Gain tracking vs. input level ITU-T G.714 Method 2 Signal to total distortion vs. input level. ITU-T G.714 Method 2 Receive Idle Channel Noise Gain relative to gain at 1020 Hz 200 Hz 300 - 3000 Hz 3000 - 3300 Hz 3300 Hz 3400 Hz 4000 Hz 4600 Hz >4600 Hz Absolute Delay Group Delay relative to DAR GTR
-0.3 -0.6 -1.6 35 29 24 11.5 -80
0.3 0.6 1.6
dB dB dB dB dB dB
3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0 -Law A-Law
4
GQR
5 6
NCR NPR GRR -0.25 -0.90 -0.9 -0.9
14 -77 0.25 0.25 0.25 0.25 0.25 -12.5 -25 -25
dBrnC0 dBm0p dB dB dB dB dB dB dB dB ms ms ms ms ms
-0.1 -0.5 -23 -41 240 750 380 130 750 -90 -90
7 8
DAR DDR
at frequency of min. delay 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz ITU-T G.714.16
9
Crosstalk
D/A to A/D A/D to D/A
CTRT CTTR
-74 -80
dB dB
AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. * Note: RxINC, refer to Control Register 1, address 00h.
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Zarlink Semiconductor Inc.
MT91L60/61
AC Electrical Characteristics for Side-tone Path Characteristics 1 Absolute path gain gain adjust = 0 dB Sym. GAS1 GAS2 Min. -17.1 -11.1 Typ. -16.5 -10.5 Max. -15.9 -9.9 Units dB dB
Data Sheet
Test Conditions RxINC = 0* RxINC = 1* M inputs to HSPKR outputs 1000 Hz at STG2=1
2
Tolerance of other side-tone settings (-9.96 to 9.96 dB) relative to output at 0 dB setting
-0.5
+/-0.2
+0.5
dB
AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. * Note: RxINC, refer to Control Register 1, address 00h.
Electrical Characteristics for Analog Outputs Characteristics 1 2 3 Earpiece load impedance Allowable earpiece capacitive load Earpiece harmonic distortion Sym. EZL ECL ED Min. 260 Typ. 300 300 0.5 Max. Units ohms pF % Test Conditions across HSPKR each pin: HSPKR+, HSPKR-
300 ohms load across HSPKR (tol-15%), VO693mVRMS, RxINC=1*, Rx gain=0 dB
Electrical Characteristics are over recommended temperature range & recommended power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. * Note: RxINC, refer to Control Register 1, address 00h.
Electrical Characteristics for Analog Inputs Characteristics 1 Maximum input voltage without overloading Codec across M+/MVIOLH 2.128 0.756 Vp-p Vp-p TxINC = 0, A/ = 0* TxINC = 1, A/ = 1* Tx filter gain=0 dB setting 50 kW M+/M2 Input Impedance ZI Electrical Characteristics are over recommended temperature range & recommended power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. * Note: TxINC, refer to Control Register 1, address 00h. to VSSA Sym. Min. Typ. Max. Units Test Conditions
24
Zarlink Semiconductor Inc.
MT91L60/61
AC Electrical Characteristics - ST-BUS Timing (See Figure 11) Characteristics 1 2 3 4 5 6 7 8 9 10 C4i Clock Period C4i Clock High period C4i Clock Low period C4i Clock Transition Time F0i Frame Pulse Setup Time F0i Frame Pulse Hold Time Delayed Frame Pulse delay after C4i rising Delayed Frame Pulse hold time from C4i rising DSTo Delay DSTi Setup Time Sym. tC4P tC4H tC4L tT tF0iS tF0iH tF0odS tF0odH tDSToD tDSTiS 20 50 50 55 50 125 Min. Typ. 244 122 122 20 Max. Units ns ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions
CL = 30 pF, 1 k load.*
50 ns 11 DSTi Hold Time tDSTiH Timing is over recommended temperature range & recommended power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. * Note: All conditions data-data, data-HiZ, HiZ-data.
tT tC4P C4i 70% 30% tDSToD 70% 30% tDSTiS DSTi 70% 30% tT F0i 70% 30% tF0odS F0od 70% 30% 64 Clock Periods NOTE: Levels refer to%VDD tF0odH tF0iS tF0iH tT tDSTiH 1 bit cell tC4H tC4L tT
DSTo
Figure 11 - ST-BUS Timing Diagram
25
Zarlink Semiconductor Inc.
MT91L60/61
AC Electrical Characteristics - SSI BUS Synchronous Timing (see Figure 12) Characteristics 1 2 3 4 5 6 7 8 9 BCL Clock Period BCL Pulse Width High BCL Pulse Width Low BCL Rise/Fall Time Strobe Pulse Width Delayed Strobe Pulse Width Strobe setup time before BCL falling Strobe hold time after BCL falling Delayed Strobe Pulse delay after BCL rising Sym. tBCL tBCLH tBCLL tR/tF tENW tENWD tSSS tSSH tDSTBR tDSTBF tDOZL tDOZH tDOLZ tDOHZ tDD tDIS tDIH 10 50 70 80 Min. 244 115 122 122 20 8 x tBCL 8 x tBCL
tBCL-80 tBCL-80
Data Sheet
Typ.
Max. 1953
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Test Conditions BCL=4096 kHz to 512 kHz BCL=4096 kHz BCL=4096 kHz Note 1 Note 1 Note 1
55 55 55 55 90 90 80
Note 1 Note 1 CL=50 pF, RL=1 K CL=50 pF, RL=1 K CL=50 pF, RL=1 K CL=50 pF, RL=1 K CL=50 pF, RL=1 K
10 Delayed Strobe Pulse hold time after BCL rising 11 Dout High Impedance to Active Low from Strobe rising 12 Dout High Impedance to Active High from Strobe rising 13 Dout Active Low to High Impedance from Strobe falling 14 Dout Active High to High Impedance from Strobe falling 15 Dout Delay (high and low) from BCL rising 16 Din Setup time before BCL falling 17 Din Hold Time from BCL falling
Timing is over recommended temperature range & recommended power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Note 1: Not production tested, guaranteed by design.
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Zarlink Semiconductor Inc.
MT91L60/61
tBCL tBCLH tR CLOCKin 70% (BCL) 30% tBCLL tDIS Din 70% 30% tDOZL Dout 70% 30% tDOZH tSSS STB 70% 30%
tDSTBR
Data Sheet
tF
tDIH
tDD
tENW
tSSH
tDOLZ tDOHZ
tDSTBF
70% STBd 30% NOTE: Levels refer to% VDD (CMOS I/O) tENWD
Figure 12 - SSI Synchronous Timing Diagram
27
Zarlink Semiconductor Inc.
MT91L60/61
AC Electrical Characteristics - SSI BUS Asynchronous Timing (note 1) (see Figure 13) Characteristics 1 Bit Cell Period 2 Frame Jitter 3 Bit 1 Dout Delay from STB going high 4 Bit 2 Dout Delay from STB going high 5 Bit n Dout Delay from STB going high Sym. TDATA Tj tdda1 tdda2 tddan 600+ TDATA-Tj 600 + (n-1) x TDATA-Tj TDATA-Tj TDATA\2 +500ns-Tj +(n-1) x TDATA TDATA\2 +500ns+Tj +(n-1) x TDATA 600+ TDATA 600 + (n-1) x TDATA Min. Typ. 7812 3906 600 Tj+600 600 + TDATA+Tj 600 + (n-1) x TDATA+Tj TDATA+Tj Max. Units ns ns ns ns ns ns
Data Sheet
Test Conditions BCL=128 kHz BCL=256 kHz CL=50 pF, RL=1 K CL=50 pF, RL=1 K CL=50 pF, RL=1 K n=3 to 8
6 Bit 1 Data Boundary 7 Din Bit n Data Setup time from STB rising
TDATA1 tSU
ns ns n=1-8
8 Din Data Hold time from STB rising
tho
ns
Timing is over recommended temperature range & recommended power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Note 1: Not production tested, guaranteed by design.
Tj
STB
70% 30% tdda2 tdha1 tdda1 70% 30% Bit 1 TDATA1 tho tsu Bit 2 Bit 3 TDATA
Dout
Din
70% 30% TDATA/2 D1 TDATA D2 TDATA D3
NOTE: Levels refer to% VDD (CMOS I/O)
Figure 13 - SSI Asynchronous Timing Diagram
28
Zarlink Semiconductor Inc.
MT91L60/61
AC Electrical Characteristics - Microport Timing (see Figure 14) Characteristics 1 2 3 4 5 6 7 8 9 10 Input data setup Input data hold Output data delay Serial clock period SCLK pulse width high SCLK pulse width low CS setup-Intel CS setup-Motorola CS hold CS to output high impedance Sym. tIDS tIDH tODD tCYC tCH tCL tCSSI tCSSM tCSH tOHZ 500 250 250 200 100 100 120 1000 500 500 Min. 100 30 120 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions
CL = 50pF, RL = 1 K *
CL = 50pF, RL = 1 K
Timing is over recommended temperature range & recommended power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Note: All conditions data-data, data-HiZ, HiZ-data.
2.0 V 0.8 V tIDS tIDH tCH SCLK tCSSI CS tCSSM tCH tCL
DATA INPUT DATA OUTPUT 2.0 V 0.8 V tODD 90% HiZ 10% Intel Mode = 0
tCYC
2.0 V 0.8 V tOHZ 2.0 V 0.8 V tCSH 2.0 V 0.8 V tCL tIDH DATA OUTPUT tIDS 2.0 V DATA INPUT 0.8 V NOTE: % refers to% VDD 2.0 V 0.8 V tCYC tODD 90% HiZ 10% Motorola Mode = 00
SCLK
Figure 14 - Microport Timing
29
Zarlink Semiconductor Inc.
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